This application is based upon and claims the benefit of Japanese Patent Application No. 2000-143303 filed on May 16, 2000, the contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a method for manufacturing a semiconductor device in which a trench is formed on a semiconductor substrate to provide an electrical isolation structure or an embedded gate therein.
2. Description of the Related Art
Recently, a semiconductor device with an electrical isolation (trench isolation) structure or a semiconductor device with an embedded gate (trench type gate) has been proposed in accordance with improved integration degrees of various semiconductor devices.
When this kind of semiconductor device is manufactured, a method shown in FIGS. 16A to 16G has been adopted. FIG. 16A is a flowchart showing the method in a stepwise manner. Specifically, referring to FIG. 16B, an etching mask 52 is formed with an opening 52a at a predetermined position by a mask formation step S101 and a mask opening step S102. Next, as shown in FIG. 16C, a trench 53 is formed on a semiconductor substrate 51 by anisotropically etching the substrate 51 in a thickness direction thereof at a trench formation step S103.
After this anisotropic etching, a thermal oxide film (sacrificial oxide film) formation step S104 and a thermal oxide film removal step S105 are successively carried out on purpose to improve the shape of the trench 53 and to remove an etching damage layer formed on the surface of the semiconductor substrate 51. Then, a mask removal step S106 is carried out to remove the mask 52 as shown in FIG. 16D. Further, at an insulation film formation step S107, as shown in FIG. 16E, an insulation film 54 is formed on the surface of the semiconductor substrate 51 including the inner wall surface of the trench 53 by thermal oxidation.
Then, a polysilicon deposition step S108 is carried out to form a polysilicon film 55 on the insulation film 54 by, for example, a CVD apparatus. Accordingly, the inside of the trench 53 is filled with polysilicon, and from this state, the polysilicon 55 is etched (etched back) at an etching step S109 so that the surface above the trench 53 is flattened. Finally, a polysilicon embedded layer 56 embedded in the trench 53 is obtained as shown in FIG. 16G.
According to this method, however, it is difficult to control an etching amount at the etching step S109. Further, a steep step may be produced in the trench 53 after performing the etching of the polysilicon film 55, due to the etching progressing at a depression 57 (see FIG. 16F) that is produced at a position corresponding to the center of the trench 53 when the polysilicon film 55 is deposited. Therefore, it is difficult to sufficiently flatten the surface above the trench 56.
To reduce the steep step produced at the edge portion of the trench due to flattening, JP-A-63-313834 and JP-A-1-107554 disclose techniques for tapering the opening portion of the trench. According to these techniques, the step produced at the edge portion of the trench can be improved; however, the techniques cannot improve (reduce) the step produced inside the trench after the flattening treatment, due to the depression produced corresponding to the center of the trench.
FIG. 17 shows a relation between the depth of the depression 57 and the thickness of the polysilicon film 55 formed by the method shown in FIGS. 16A to 16G. As shown in FIG. 17, the depth of the depression 57 is decreased as the thickness of the polysilicon film 55 is increased and then tends to saturate at a specific magnitude, although the relation somewhat depends on width W of the trench 53. That is, the depth of the depression 57 is reduced as the thickness of the polysilicon film 55 is increased; however, there exists a limitation in this method, and it is difficult to flatten the surface portion of the trench 53 only by embedding polysilicon therein.
As another conventional technique for flattening a surface of a trench formed on a semiconductor substrate, a manufacturing method is conceivable, which is shown in FIGS. 18A to 18H. FIG. 18A is a flow chart showing the manufacturing method in a stepwise manner. Specifically, after an oxide film formation step S201 is carried out to form an oxide film 59 on a semiconductor substrate 58, a mask formation step S202 for forming a mask and a mask/oxide-film opening step S203 utilizing a photolithography technique are successively carried out. Accordingly, an etching mask 60 having an opening 60a is provided. Further, as shown in FIG. 18B, a trench 61 is formed at a trench formation step S204 involving anisotropic dry etching using the mask 60.
From this state, a thermal oxide film formation step S205 and a thermal oxide film removal step S206 are successively carried out to improve the shape of the trench 61 as shown in FIG. 18C. After that, at an insulation film formation step S207, as shown in FIG. 18D, an insulation film 59 is formed inside the trench 61 with the mask 60, by thermal oxidation. Then, at a polysilicon deposition step S208, as shown in FIG. 18E, a polysilicon film 62 is deposited on the surface of the substrate 58 by, for example, a CVD apparatus, thereby filling the inside of the trench 61 with polysilicon. After that, referring to FIGS. 18F and 18G, for example, a polishing step S209 for removing an extra part of the polysilicon on the semiconductor substrate 58 by CMP (Chemical Mechanical polish) or the like, and a mask removal step S210 for removing the mask 60 are carried out. Further, the part of the polysilicon film 62 projecting from the substrate surface as shown in FIG. 18G is etched at an etching step S211 to remove the step between the surface above the trench 61 and the substrate surface, thereby forming a polysilicon embedded layer 63 embedded in the trench 61 as shown in FIG. 18H.
According to the second conventional technique shown in FIGS. 18A to 18H, although the polysilicon film 62 filling the trench 62 has a depression 64 at a position corresponding to the center of the trench 61 as shown in FIG. 18E, the finally obtained surface above the trench 61 can be flattened without being affected by the depression 64. However, it is difficult to control the degree of parallelization between the substrate surface and the polished surface during the polishing step. Because of this, the projecting part of the polysilicon projecting from the substrate surface shown in FIG. 18G is liable to have large variation in height. This makes it difficult to flatten the surface above the trench. The etching of the projecting part is also difficult to be controlled, resulting in difficulty of flattening as well.
Further, in the case where the projecting part of the polysilicon is etched by dry-etching that is relatively easily controlled, the substrate surface, especially the property of the insulation film 59 disposed in the vicinity of the opening of the trench 61 is deteriorated by the etching, resulting in deterioration in isolation withstand voltage when trench isolation is provided with the trench 61. This also results in deterioration in gate withstand voltage in case where the trench 61 is used for an embedded gate (trench type gate).
Thus, in the conventional manufacturing methods, the surface above the trench cannot be flattened sufficiently and may have steps, otherwise, the flattened surface may have variations. Because of this, in the case of the trench isolation, wiring members are difficult to be disposed above the trench, or wiring members disposed above the trench are liable to deteriorate due to the steps or large variations on the surface. In the case of the trench type gate, an electric field is liable to concentrate on the steps on the trench, the degree of electric field concentration varies within the substrate surface, and accordingly characteristics of the device deteriorates.
The present invention has been made in view of the above problems. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of improving flatness of a surface of a semiconductor substrate above a trench securely.
According to the present invention, after a polysilicon film is formed on a semiconductor substrate to fill an inside of a trench, a selective thin film is formed on the polysilicon film. The selective thin film has etching selectivity with respect to the polysilicon film when the polysilicon film is etched. Then, an etch-back step is successively performed to the selective thin film and the polysilicon film.
Accordingly, the polysilicon film can be etched with a self-aligning mask that can be formed from a part of the selective thin film and left in a depression of the polysilicon film above the trench at the etch-back step of the selective thin film. The self-aligning mask can suppress etching of the polysilicon film above the trench, and prevent steps from being produced above the trench due to the depression. As a result, the surface of the semiconductor substrate above the trench can be flattened easily and sufficiently.